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NXP Semiconductors /LPC43xx /GIMA /CAP1_2_IN

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Interpret as CAP1_2_IN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOT_INVERTED)INV 0 (NO_EDGE_DETECTION)EDGE 0 (DISABLE__SYNCHRONIZ)SYNCH 0 (DISABLE_SINGLE_PULSE)PULSE 0 (CTIN_4)SELECT0RESERVED

SELECT=CTIN_4, EDGE=NO_EDGE_DETECTION, INV=NOT_INVERTED, PULSE=DISABLE_SINGLE_PULSE, SYNCH=DISABLE__SYNCHRONIZ

Description

Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)

Fields

INV

Invert input

0 (NOT_INVERTED): Not inverted.

1 (INPUT_INVERTED): Input inverted.
EDGE

Enable rising edge detection

0 (NO_EDGE_DETECTION): No edge detection.

1 (RISING_EDGE_DETECTIO): Rising edge detection enabled.
SYNCH

Enable synchronization

0 (DISABLE__SYNCHRONIZ): Disable synchronization.

1 (ENABLE__SYNCHRONIZA): Enable synchronization.
PULSE

Enable single pulse generation.

0 (DISABLE_SINGLE_PULSE): Disable single pulse generation.

1 (ENABLE_SINGLE_PULSE): Enable single pulse generation.
SELECT

Select input. Values 0x3 to 0xF are reserved.

0 (CTIN_4): CTIN_4

1 (USART0_RX_ACTIVE): USART0 RX active

2 (T1_CAP2): T1_CAP2
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data